Two goals associated with SRAM cell design include reducing the silicon area consumed by the cells, i.e. increasing the density of the cells in a SRAM device, and include increasing the operating speed of the cells, i.e. decreasing the time required to access a cell to perform a read or write operation. A high density SRAM cell is realized by using fewer transistors. A number of SRAM cell designs have been proposed.
Conventional CMOS SRAM cells essentially consist of a pair of cross-coupled inverters as the storage flip-flop or latch, and a pair of pass transistors as the access devices for data transfer into and out of the cell. SRAM cell designs have progressed from a four transistor SRAM cell illustrated in FIG. 1 and a six transistor SRAM cell illustrated in FIG. 2 to a loadless four transistor SRAM cell illustrated in FIG. 3. The four transistor SRAM cell or NMOS resistor load cell, hereinafter referred to as the 4-T SRAM cell, occupies a relatively small area, but the fabrication of the passive loads involves relatively complex steps. One embodiment of the 4T-SRAM cell has one load resistor for each of the pull-down NMOS transistors, and another embodiment shares one load resistor for the two transistors. The 4-T SRAM cell incurs steady state standby DC power dissipation and can inadvertently become unstable. Additionally, the resistive load inverters used in the 4-T SRAM cell cause asymmetrical switching transients. The six transistor SRAM cell, hereinafter referred to as the 6-T SRAM cell, incurs less power dissipation, is more stable, and has more symmetrical switching transients; but it is approximately 30% to 40% larger than the 4-T SRAM cell, and thus consumes more chip surface area and is more costly to fabricate.
The problems associated with the 4-T SRAM cell and the 6-T SRAM cell have led to the development of the loadless four transistor SRAM cell, hereinafter referred to as the LL4TCMOS SRAM cell. The LL4TCMOS SRAM cell comprises a pair of NMOS pull-down transistors and a pair of PMOS access transistors. The subthreshold leakage of the access transistors replace the load resistor(s) in the 4-SRAM cell and the load transistors in the 6-T SRAM cell. The LL4TCMOS SRAM is relatively small, but is not as small as the 4-T SRAM cell because it incorporates CMOS devices. The LL4TCMOS SRAM cell design suffers from stability margin problems caused by leakage current and noise.
Other SRAM cell design proposals include two transistor SRAM cell designs based on bipolar latch-up. One cell design incorporates vertical transistors, while another design that requires a somewhat larger area incorporates planar devices. Cell designs based on bipolar latch-up are disclosed in U.S. Pat. No. 6,104,045, entitled HIGH DENSITY PLANAR SRAM CELL USING BIPOLAR LATCH-UP AND GATED DIODE BREAKDOWN, and U.S. Pat. No. 6,128,216, entitled HIGH DENSITY PLANAR SRAM CELL WITH MERGED TRANSISTORS. Both of these patents are assigned to Applicant's assignee, and are hereby incorporated by reference.
Therefore, there is a need in the art to provide a SRAM cell, and read and write techniques for the same, that overcomes the shortcomings of the above SRAM designs and that achieves the goals of increased density and increased operating speed.